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Dr. Somesh Kumar

Dr. Somesh Kumar

Assistant Professor , Department of Electrical and Electronics Engineering

Email: somesh@iiitm.ac.in


Phone: +91-7009594389


Experience: 14 Years


Address:

Room No. C-210, Electrical & Electronics Engineering (EEE) Department, ABV- Indian Institute of Information Technology & Management, Gwalior, Madhya Pradesh, India- 474015.


Personal Web Page: https://sites.google.com/iiitm.ac.in/skumar/home?a


Dr. Somesh Kumar

Biography

Dr. Somesh Kumar joined the Atal Bihari Vajpayee-Indian Institute of Information Technology and Management (ABV-IIITM), Gwalior in 2019, where he is currently an Assistant Professor in the department of Electrical and Electronics Engineering. Before joining IIITM Gwalior, Dr. Kumar was an Assistant Professor at the Indian Institute of Information Technology Nagpur (IIITN), Nagpur. He has established the Interconnect Focus Lab (IFL), Drone Lab, High Frequency Simulation Lab, HDL Lab, Digital and Analog Electronics Lab for UG and PG students.  

Dr. Kumar received the B. Tech. degree in Electronics and Telecommunication Engineering from Kurukshetra University (Ch. Devilal Memorial Government Engineering College) in 2009, the M. Tech degree in VLSI Design & CAD from Thapar University in 2012 under the supervision of Prof. Ravi Kumar. He did Ph. D. degree in Electrical Engineering from Indian Institute of Technology Ropar (IIT Ropar) in 2018. His Ph. D. supervisor was Prof. Rohit Y. Sharma - with whom he learned the rudiments of high-speed interconnect design and 3D IC Design. During his doctoral studies, he worked on modeling, fabrication and performance benchmarking of on-chip and chip-to-chip interconnects considering surface roughness. His current research interests include Application of Machine Learning in the Design and Analysis of Interconnects and Packages, Modeling and Fabrication of High-Speed Interconnects, 3D Integration and Design of Through-Silicon-Via (TSV), Antenna for 5G And 6G Applications, Interconnect Architecture for Network-On-Chips, Digital and Analog VLSI Design, Flexible Devices, Nanoscale Device Modelling and Simulation, Reversible Circuits, IOT-Based Hardware Design and Biosensors.

He is a referee for several journals including IEEE Transactions on Electromagnetic Compatibility, IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Components, Packaging and Manufacturing Techniques, IET Digital & computer techniques and Journal of Supercomputing. He is a Senior Member of the IEEE and convener of IEEE student branch at ABV-IIITM, Gwalior. He is also GIAN local coordinator of IIITM Gwalior. He has conducted more than 100 national and international events since 2019 to till date.

Research Interest


  • Application of Machine Learning in the Design and Analysis of Interconnects and Packages.
  • Modeling And Fabrication of High-Speed Interconnects.
  • 3D Integration and Design of Through-Silicon-Via (TSV).
  • Antenna for 5G And 6G Applications.
  • Micro and Nanotechnology Manufacturing.
  • Design and Optimization of Graphene-Based Nanoelectronic Circuits.
  • Interconnect Architecture for Network-On-Chips.
  • Digital and Analog VLSI Design.
  • Flexible Devices.
  • Reversible Circuits
  • IOT-Based Hardware Design
  • Biosensors
  • Nanoscale Device Modelling and Simulation

Taught Courses


  • Electronic Devices and Circuits
  • Digital Electronic Circuits
  • Analog IC Design
  • Microelectronic Circuit Design
  • VLSI Design
  • IC Technology
  • Information and Communication Techniques
  • Fundamentals of IoT
  • Synthesis of Digital Design
  • System Level Design and Modelling
  • Electronic Devices and Circuits
  • Digital VLSI Design
  • Digital Electronic Circuits Lab
  • Electronic Devices and Circuits Lab
  • HDL Lab

E-Learning Courses Prepared


Ph.D., M.Tech. and B.Tech. Students Guided


  • Ph.D.: 3 (ongoing)
  • M.Tech.: 27
  • B.Tech.: 51

Research Projects Undertaken


  • DST, SERB, SRG project entitled “Design and Modeling of Ultra-Scaled Copper-Graphene Hybrid On-Chip Interconnects for Low Power and High-Speed IC Applications with Machine Learning”, (13th Jan 2021, 15.20Lakh); PI; Ongoing.
  • TIIC, TIDE 2.0 Scheme, “Development of IOT Based Smart isolation/ Quarantine Center to combat COVID-19”, (Nov. 2020, 3.5Lakh); Co-PI; Completed.
  • TIIC, TIDE 2.0 Scheme, “An IoT based Complete Sanitization System for the Dispensary of ABV-IIITM Gwalior”, (Jan. 2022, 3Lakh); PI; ongoing
  • DST, SERB, Karyashala project entitled “Recent Trends in VLSI Devices, Circuits and Applications”, (Dec. 2021, 5.00Lakh); PI; Completed
  • DST, SERB, Karyashala project entitled “Advances in Nanoscale Transistors for Next-Generation Applications”, (Dec. 2021, 5.00Lakh); PI; Ongoing
  • DST, SERB, Karyashala project entitled “Design and Fabrication of Hybrid Flexible Antennas for 6G and beyond Applications”, (Dec. 2021, 5.00Lakh); Co-PI; Completed
  • INUP project entitled “Fabrication and electrical characterization of Micro (chip to chip) and Nanoscale (on chip) Cu and Ag-Cu composite interconnects structures” at IIT Bombay (May 2016-July 2017); PI; Completed.

Publications


  1. Kumar et al., “Optimal Design of High-Speed PCB Interconnects using Electrical-Thermal Co-Simulation”, IEEE Transactions on Signal and Power Integrity, 2023 (under review).  
  2. Kumar et al., “Knowledge Distillation Based Few-Shot Learning for Intrusion Detection”, Multimedia Tools and Applications, Springer, 2023 (under review)
  3. Kumar et al., “Automated Passive Income from Stock Market Using Machine Learning and Big Data Analytics with Security Aspects”, Concurrency and Computation: Practice and Experience, 2023 (under review).
  4. Kumar et al., “High-speed Interconnects: History, Evolution, and the Road Ahead”, IEEE Microwave Magazine, vol. 23, no. 8, pp. 66-82, 2022. (SCI, IF-3.062); DOI: 10.1109/MMM.2021.3136268.
  5. Kumar et al., “Knowledge-Based Neural Networks for Fast Design Space Exploration of Hybrid Copper-Graphene On-Chip Interconnect Networks”, IEEE Tran. on Electromagnetic Compatibilityvol. 64, no. 1, pp. 182-195, 2022. (SCI, IF: 2.036); DOI: 10.1109/TEMC.2021.3091714
  6. Kumar et al., “Design and Implementation of Low Power, High-speed Configurable Approximation 8-bit Booth Multiplier”, Journal of Circuits, Systems, and Computers (JCSC), 2022 (in press, pre-print available). (SCI, IF-1.278); DOI: https://doi.org/10.1142/S0218126622502966
  7. Kumar et al., “Coverage Hole Detection Using Social Spider Optimized Gaussian Mixture Model”, Journal of King Saud University - Computer and Information Sciences (Elsevier), 2021 (in press, pre-print available). (SCI, IF: 8.839); DOI: https://doi.org/10.1016/j.jksuci.2021.12.010.
  8. Kumar et al., “Disease Detection in Apple Leaves Using Deep Convolutional Neural Network,” Agriculture MDPI Journal, pp. 1-23, vol. 11, no. 7: 617, 2021. (SCI, IF-3.408); DOI: https://doi.org/10.3390/agriculture11070617
  9. Kumar et al., “Analysis and Implementation of Threat Agents Profiles in Semi-Automated Manner for a Network Traffic in Real-Time Information Environment,” Electronics MDPI Journal, pp. 1-18, vol 10, no. 15: 1849, 2021. (SCI, IF-2.690); DOI: https://doi.org/10.3390/electronics10151849.
  10. Kumar et al., “A Survey on Layer-wise Security attacks in IoT: Attacks, Countermeasures, and Open-Issues,” Electronics MDPI Journal, pp. vol. 10, no. 2365, 2021. (SCI, IF-2.690); DOI: https://doi.org/10.3390/electronics10192365
  11. Kumar et al., “A Temperature and Dielectric Roughness-Aware Matrix Rational Approximation (MRA) Model for the Reliability Assessment of Copper-Graphene Hybrid On-Chip Interconnects”, IEEE Tran. on Components, Packaging and Manufacturing Technology, vol. 10, no. 9, pp. 1454-1465, 2020. (SCI, IF-1.922); DOI: 10.1109/TCPMT.2020.3004414
  12. Kumar et al., “Analyzing Crosstalk-induced Effects in Rough On-chip Copper Interconnects”, IEEE Tran. on Components, Packaging and Manufacturing Technology, vol. 9, no. 10, pp. 1984-1992, 2019. (SCI, IF-1.922); DOI: 10.1109/TCPMT.2019.2941871
  13. Kumar, and R. Sharma, “Design of energy-aware interconnects for next generation micro systems”, CSI Transactions on ICT (Springer), vol. 7, no. 3, pp. 215-220, 2019. DOI: 10.1007/s40012-019-00239-6
  14. Kumar, and R. Sharma, “Investigating the Role of Interconnect Surface Roughness towards the Design of Power-Aware Network on Chip”, IET Computers and Digital Techniques, vol. 13, no. 1, pp. 49-56, 2019. (SCI, IF-0.906); DOI: https://doi.org/10.1049/iet-cdt.2018.5067
  15. Kumar, and R. Sharma, “Chip-to-Chip Copper Interconnects with Rough Surfaces: Analytical models for Parameter Extraction and Performance Evaluation”, IEEE Tran. on Components, Packaging and Manufacturing Technology, vol. 8, no. 2, pp. 286-299, 2018. (SCI, IF-1.922); DOI: 10.1109/TCPMT.2017.2774252
  16. Kumar, and R. Sharma, “Analytical Model for Resistivity and Mean Free Path in On-Chip Interconnect with Rough Surfaces”, IEEE Tran. on Emerging Topics in Computing, vol. 6, no. 2, pp. 233-243, 2018. (SCI, IF-6.595); DOI: 10.1109/TETC.2016.2597542
  17. Kumar, and R. Sharma, “Analytical Modeling and Performance Benchmarking of On-Chip Interconnects with Rough Surfaces”, IEEE Tran. on Multi-Scale Computing System, vol. 4, no. 3, pp. 272-284, 2018. DOI: 10.1109/TMSCS.2017.2696941
  18. Kumar and Monika, “Study of Effect of Variations in slot dimensions on Fractal Patch antenna Performance”, International Journal of Computers & Technology, vol. 5, no. 1, pp. 41-48, 2013.
  19. Kumar and R. Kumar, “A 1.8V and 2GHz Inductively Degenerated CMOS Low Noise Amplifier”, International Journal of Electronics Communication and Computer Technology, vol. 2, no. 4, pp. 150-154, 2012.
  20. Kumar and Kuldeepak, “A 0.18µm and 2GHz CMOS Differential Low Noise Amplifier”, International Journal of Electronics Communication and Computer Technology, vol. 2, no. 4, pp. 155-158, 2012.

International Conferences


  1. Kumar et al., “Exploring Real-Time scenarios and isolated execution via a Remote Code Executor,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).
  2. Kumar et al., “Reconfigurable Antennas: A new paradigm for reliable 5G and 6G communications,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted). 
  3. Kumar et al., “An Interactive Ride-Sharing System via Web Application,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).     
  4. Kumar et al., “Crop Recommendation using Machine Learning and Plant Disease Identification using CNN and Transfer-Learning Approach,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).      
  5. Kumar et al., “Meals On Wheels : A Platform To Connect Tiffin Services to Users,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).
  6. Kumar et al., “PlantKart: Connecting Nurseries to everyone,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).
  7. Kumar et al., “Medical Waste Classification using Deep Learning and Convolutional Neural Networks,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).
  8. Kumar et al., “NGO Portal - A Platform to connect NGOs with prospective members,” in proc. IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI), 2022 (accepted).
  9. Kumar et al., “Fraud Detection on Bank Payments Using Machine Learning,” in proc. IEEE International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-4
  10. Kumar et al., “Disease Predictor Using Random Forest Classifier,” in proc. IEEE International Conference for Advancement in Technology (ICONAT), 2022, pp. 1-4
  11. Kumar et al., “Design and Comparative Valuation of an MSML Based Low Power Content Addressable Memory Cell”, in proc. IEEE IBSSCIndia, 2021.
  12. Kumar et al., “Songs Recommendation using Context-Based Semantic Similarity between Lyrics”, in proc. IEEE INDISCONIndia, 2021.
  13. Kumar et al., “Quantum Cost-Efficient Design of Synchronous Reversible Shift Registers using Reversible Logic”, in proc. IEEE IBSSCIndia, 2021.
  14. Kumar et al., “Design and Performance Benchmarking of Dual Gate Flexible Bilayer Graphene FETs”, in proc. IEEE IBSSCIndia, 2021.
  15. Kumar et al., “Smart IoT-based Water Monitoring System using Redundancy Elimination Strategy”, in proc. IEEE IBSSCIndia, 2021.
  16. Kumar et al., “Temperature and Dielectric Surface Roughness Dependent Performance Analysis of Cu-Graphene Hybrid Interconnects”, in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS)China, 2020.
  17. Kumar et al., “2D- Discrete Cosine Transform based Dynamically Controllable Image Compression Technique”, in proc. IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2020.
  18. Kumar et al., “Estimating Per-Unit-Length Resistance Parameter in Emerging Copper-Graphene Hybrid Interconnects via Prior Knowledge Accelerated Neural Networks”, in proc. IEEE EPEPS, San Jose, USA, 2020.
  19. Kumar and Shivangi Gupta, “A Novel Perspective in Designing a Low Quantum Cost Synchronous Reversible Counters”, in proc. IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era, Morocco, Marrakech, Morocco, 2020, pp. 1-6.
  20. Kumar et al., “Role of Grain Size on the Effective Resistivity of Cu-Graphene Hybrid Interconnects”, in proc. IEEE Electronic Components and Technology Conference (ECTC), Florida, US, pp. 1-4, 2020.
  21. Kumar et al., “Temperature-Aware Compact Modeling for Resistivity in Ultra-Scaled Cu-Graphene Hybrid Interconnects”, in proc. IEEE Workshop on Signal and Power Integrity (SPI), Cologne, Germany, 2020.
  22. Kumar et al., “Malaria Parasite Recognition in Thin Blood Smear Images using Squeeze and Excitation Networks”, in proc. IEEE CICT, Allahabad, India, pp. 1-5, 2019.
  23. Kumar et al., “Crosstalk Analysis for Rough Copper Interconnects considering Ternary Logic” in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS)Chandigarh, India, 2018, pp. 1-3.
  24. Kumar et al., “A Shortest Path Algorithm for 3D Integrated Circuit TSV Assignment” in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS)Chandigarh, India, 2018.
  25. Kumar et al., “Investigating the Role of Surface Roughness on the Performance of Through Silicon Vias”, in proc. IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2017, pp. 1-4.
  26. Kumar, and R. Sharma, “Performance Modeling and Broadband Characterization of Chip-to-Chip Interconnects with Rough Surfaces”, in proc. IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2016, pp. 629-632.
  27. Kumar, and R. Sharma, “Design Space Exploration of Nanoscale Interconnects with Rough Surfaces”, in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS), Seoul, South Korea, 2015, pp. 125-128.
  28. Kumar et al., “A High-k, Metal Gate Vertical-Slit FET for Ultra-Low Power and High-Speed Applications”, in proc. IEEE International India conference (INDICON), New Delhi, India, 2015, pp. 1-5.
  29. Kumarand Sudha, “Design of Low Power, High Gain LNA for WCDMA range and Parameters Extraction using Artificial Neural Network (ANN), in proc. IEEE Power, Communication and Information Technology (PCITC), Bhubaneshwar, India, 2015, pp. 436-441.
  30. Kumar et al., “Analytical Model for Design of Complementary Inverter using Floating Gate Graphene Field Effect Transistors”, in proc. ISVLSI, Tampa, Florida, USA, 2014, pp. 148-153.
  31. Kumar et al., “Design Space Exploration of Through Silicon Vias for High-Speed, Low Loss Vertical Links”, in proc. IEEE Electrical Design of Advanced Packaging and System Symposium (EDAPS), Bangalore, India, 2014, pp. 9-12.
  32. Kumar et al., “Low Power CMOS Current Reuse Low Noise Amplifier at 2.4 GHz Frequency”, in proc. IEEE International conference on research and development prospects on Engineering and technology, Tamilnadu, India, 2013, pp. 68-70.

National Conference


  1. Kumar, “Fast Adders Synthesis and Simulation using VHDL”in proc. National Conference on Latest Advancement in Science, Engineering and Research 2011 (LASER’11), Bhatinda, India, 2011, pp. 140-143.

Patent Filed/Granted


Filed an Indian Patent titled “Machine Learning-Based Real-time Medical Emergency and Health-Crisis Management Ecosystem” Feb 2022. (Filing Number: 202221006822)

Book/Book Chapters

  1. S. Kumar, Chapter 5: “High Speed Nano Scale Interconnects” in Book Nanoscale Semiconductor: Materials, Devices and Circuits” CRC Press, Taylor & Francis, 2022. ISBN No. 9781003311379
  2. S. Kumar "Neural Networks for Fast Design Space Exploration of On-Chip Interconnect Networks" in Book "Emerging Interconnect Technologies for Integrated Circuits and Flexible Electronics" Springer, 2023.

Academic Qualifications


Degree

Year

Subject

University/Institution

PhD

2018

VLSI Interconnects Modelling

IIT Ropar, India

M.Tech.

2012

VLSI Design and CAD

Thapar University, Punjab, India

B.Tech.

2009

Electronics and Communication Engineering

CDLMGEC, Kurukshetra University, India

Selected Publications: (2025-2026)


  1. Y. P. Dwivedi, R. Chowdhury and S. Kumar, "Circularly Polarized Millimeter-Wave Antennas: Recent Developments, Design Challenges, and Future Directions," IEEE Access, vol. 14, pp. 58043-58064, 2026.

  2. V. Agarwal, and S. Kumar, “Thermal-Aware Modeling of Mean Free Path and RLC Per-Unit-Length Parameters for Borophene On-Chip Interconnects,” Journal: physica status solidi (a) applications and materials science, vol. 223, no. 7, 2026.

  3. V. Agarwal, and S. Kumar, “Analytical Models for Mean Free Path and Resistivity of Borophene for On-Chip Interconnects,” Journal of Science: Advanced Materials and Devices, vol. 11, no. 1, 2026.

  4. S. Kumar and M. Poonia, “A Novel Graph Based Algorithm to Counter Sybil Attacks in Reputation Systems Built on Blockchain”, International Journal for Global Academic & Scientific Research (IJGASR), vol. 4, no. 4, pp. 15–36, Jan. 2026.

  5. Abhishek, S. Kumar, and M. Pattanaik, “A novel spatio-topological embeddings for efficient & model-free redundant node placement in 6G IoT networks,” Telecommunication Systems, vol. 88, no. 127, 2025.

  6. Monika, P. Uchariya, P. Ranjan, and S. Kumar, “Machine learning assisted frequency reconfigurable concentric split ring resonator inspired antenna for sub-6 GHz 5G and IEEE 802.11ba/Be applications,” AEU - International Journal of Electronics and Communications, vol. 200, 2025.

  7. J. K. Rai, S. Yadav, A. K. Dwivedi, V. Singh, P. Ranjan, A. Sharma, S. Kumar and S. Pandey, “Machine learning driven design and optimization of a compact dual Port CPW fed UWB MIMO antenna for wireless communication”, Scientific Reports 15, 13885, 2025.

  8. G. Sharma, S. Vidalis, P. Mankar, N. Anand, M. Poonia, S. Kumar, “Automated Passive Income from Stock Market Using Machine Learning and Big Data Analytics with Security Aspects”, Multimedia Tools and Applications, Springer, vol. 84, pp 10109–10136, 2025.

  9. Y. P. Dwivedi, R. K. Singh, A. Gupta, P. Ranjan, S. Kumar, and R. Chowdhury, “Compact multiband SIW monopole antenna with crescent-shaped slot for Ka-band and 5G FR2 applications,” in Proc. IEEE Microwaves, Antennas and Propagation Conf. (MAPCON), Kochi, India, Dec. 14–18, 2025.

  10. Avneesh Singh, Pinku Ranjan and Somesh Kumar, “ANN-Based Surrogate Modelling Framework for Repeater Optimization in Multi-Layer Graphene Nanoribbon Interconnects under Process Variation”, in proc. IEEE Electronics Packaging Technology Conference (EPTC), Singapore, 2025, pp. 1-7, doi: 10.1109/EPTC67330.2025.11392278.

Competitive Grant(s):


Sl

Grant (Project/ Consultancy)

Funding Agency

PI/Co-PI

1

Modeling & simulation of packaging effects on MMIC die Performance in HTCC-based RF package at microwave frequencies (S-Band to Q Band)

ISRO

PI

2

Investigation of MgO Nanosheets and Nanoribbons for Spintronic devices

ACPL

Co-PI

3

Design and Implementation of Visible Light Integrated Sensing and Communication Systems for 6G and Beyond

ACPL

Co-PI

4

Design of Compact MIMO Circularly Polarized Antenna for Next-Generation Wireless Communications

VSSPL

PI

5

Design and Modeling of Ultra-Scaled Copper-Graphene Hybrid On-Chip Interconnects for Low Power and High-Speed IC Applications with Machine Learning

DST

PI

6

An IoT based Complete Sanitization System for the Dispensary of ABV-IIITM Gwalior

DST

PI

7

Development of IOT Based Smart isolation/ Quarantine Center to combat COVID-19

DST

Co-PI

Faculty Development / Management Development / Workshops / Conferences:


SN

Title

Period

Sponsoring Organization

Venue

From

To

 

1

IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI-2026)

12/3/26

14/3/25

IEEE

ABV-IIITM Gwalior

2

HACKSAGON-2026

3/4/26

5/4/26

IEEE

ABV-IIITM Gwalior

3

IEEE IATMSI-2025

6/3/25

8/3/25

IEEE

ABV-IIITM Gwalior

4

FDP on Evolution and Trends in Nanoscale Devices and Packaging Technology

4/9/25

11/9/25

EICT Academy

ABV-IIITM Gwalior

3.

 FDP on AI and IoT for Cross-Sectoral Innovation: Bridging Agriculture, Finance, and Healthcare

25/8/25

31/8/25

Self

ABV-IIITM Gwalior

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